Not Applicable
Not Applicable
1. Field of the Invention
This invention relates generally to a method, device and system for semiconductor wafer transfer in an automated wafer transfer system (WTS) for wafer processing.
2. Description of the Related Art
The semiconductor industry continues a predictable trend toward higher densities of the features within integrated circuits. From the 10-micron range in 1970, feature dimensions of 0.13-micron are now common. These extremely high densities have driven the need for extremely clean processes within semiconductor fabrication facilities. The concern for contamination has been only one force driving the automation of processes and the removal of human operators from the processing area.
As the features within devices have become smaller, the devices themselves have grown larger to accommodate greater functional complexity. With that has come a growth in the size of wafers. Larger wafers allow for more devices with a smaller percentage of devices being lost at the circumference of the wafer. As more devices are produced with fewer wafers being handled, the manufacturing cost of each device can be reduced.
When the first generation of microcomputer chips reached production volumes, they were being fabricated on 2-inch diameter wafers. In 1994 sales of 200-mm (8-inch) diameter wafers began and those involved in industry standards agreed that 300-mm (12-inch) would be the next step in size. In 1998, the first robots for handling 300-mm wafers came into being, although hardware standards for wafer carriers, load ports and other now common component sub-assemblies of Automated Material Handling Systems would not be published for another two years. The industry has now settled on transport carriers containing 25 of the 300-mm wafers. This means that a full carrier weighs significantly more than humans can carry safely and reliably. Also, considering that a single finished wafer may be valued at more than $200,000, extreme care is required in the handling of wafers to avoid even the slightest damage, furthering the need for robotic assistance. Not many human operators can be trusted to repetitiously lift a heavy carrier containing $5-million of product at the end of a long work shift, but this is of lesser concern for a tireless robot.
Given these and other considerations, a high level of automation is employed for handling semiconductor wafers during fabrication. The processing environment is commonly arranged as a wafer transfer system (WTS) that supplies wafers to a process section, often referred to as a bench, having its own separate process automation and wafer handling.
As the semiconductor industry has developed into a commodity market with high volumes and low margins, it has become extremely important to create and adopt standards wherever possible. One such standard, developed specifically for use with 300-mm wafers, is a transport carrier and storage device known as a Front Opening Unified Pod, or FOUP. Containing as many as twenty-five 300-mm wafers, a FOUP is a sealed case with a locked panel. The panel can be removed by automation at the WTS for extraction of the wafers while supporting the wafers in an ultra clean environment.
Previous generations of wafer carriers for the smaller (four, six and eight inch) wafers are known as Standard Mechanical Interface (SMIF) pods. In a SMIF pod, the wafers are transported on edge, in a wafer-vertical orientation. This facilitates transfer of wafers between tools since processing applications require that the WTS position the wafers vertically for hand-off to a process bench. Though cassettes of 300-mm wafers are preferably transferred to the bench automation in a wafer-vertical configuration, a FOUP holds wafers in a horizontal orientation, requiring that the wafers be tilted before being presented to the process bench. Once inside a clean chamber, wafers have historically been transferred in open containers, such as cassettes, using various transfer systems.
Because of the high capital cost associated with a wafer fabrication facility, two other considerations come into play. One is the cost per square foot, particularly of the floorspace that lies within cleanrooms. The other is the productivity of that floorspace. Productivity alone is usually measured as throughput in units of wafers per hour (wph), while together the two issues can be quantified as wafers per hour per square-foot. Typically, semiconductor device manufacturers prohibit increases in equipment footprint unless there is a proportional increase in wafer processing throughput.
Considerations for Improvement over the Related Art
Much of the prior art related to the movement of semiconductor wafers focuses on transfer of the wafers from one processing station to the next within the process bench. In many such systems, wafers are loaded into the system one at a time, through an air-locked slit to reduce the chance of introducing contaminants to the bench. Other systems accept a transport carrier, such as a SMIF or FOUP, mounted to an air-locked panel, from which wafers are removed, one or more at a time, for processing.
It is important that the WTS automation be fast and reliable so that the bench has a constant supply of wafers readily available for processing. Typically, the industry has seen WTS throughput in the range of 200-300 wph. This means that the WTS in such a scenario can supply the bench with eight to twelve 25-wafer cassettes every hour.
In order to increase throughput rates, equipment manufacturers have added a buffer to the wafer handling tool. The buffer serves as a storage area for wafers until they are ready to be processed or removed from the tool. This local stock of wafers reduces the risk of the processing system running idle for lack of wafers. U.S. Pat. No. 6,079,927 xe2x80x9cAutomated wafer buffer for use with wafer processing equipmentxe2x80x9d shows one approach for stocking wafers within their over-sized protective FOUPs at the front-end (operator side) of the WTS. Other systems may provide buffered storage in more space-efficient open cassettes at the back-end of the WTS, nearer the process bench. Separate buffering equipment, due to the physical space it requires, increases the footprint of the entire processing system. It also introduces additional interfacing requirements. However, buffers can significantly increase throughput by being an ever-ready source of wafers for the bench. This trade-off is evaluated by individual chip manufacturers based on their specific process and application requirements. Without regard to the presence or absence of a buffer, or where such optional buffer might reside, it is the task of a WTS to transfer wafers from the FOUP to the process bench and back while presenting each wafer in the proper orientation according to the interface requirements of each port.
As buffer systems have grown in capacity, they have also grown in physical dimensions. The resulting distances involved in transporting wafers and their cassettes have been traversed using mechanisms appropriate to the dimensions. These mechanisms have included trolleys, and gantry and crane systems. Even robotic carts have been used to cover longer distances guided by wire or tape on floors. Much of the prior art describes such mechanisms as they are used not only for external buffer storage but also within the process automation itself for transferring wafers from one process station to the next.
While high production throughput rates are important to chip manufacturers, so is product quality. Process analysis is a key element in determining the quality of the product that is output from the system. In order to gather data for the process side of the system, it is required that all wafers be subjected to the chemicals in the same manner. This may be accomplished in three ways.
In a first means, the wafers are introduced to the chemicals in a vertical position as mentioned above. For wet processing applications, this ensures that the liquid flow of chemicals around the wafers is equivalent and that all wafers are exposed to the chemicals for equal amounts of time.
In a second means, each wafer is manufactured with a 3 mm notch cut into its circumferential edge. Aligning the wafers in the same position relative to a known datum allows the process engineers to analyze similar data for each wafer. Wafers are placed in FOUPs randomly; the wafers are not aligned and the position of the notch is unknown. A notch alignment function may or may not be required, depending on customer or process requirements. When required, it is the responsibility of the WTS to perform notch alignment, ensuring that all wafers are similarly positioned before the bench processes them. Most WTS designs that do provide notch alignment have a separate location for this functionality. Beyond increasing the floorspace requirements, the separate location and the associated moves to transfer the wafer to and from that location affect throughput of the tool and introduce additional potential for damage to the wafer. The added feature of performing notch alignment requires time and extreme caution, which negatively affects throughput rates. However, in order to be sure that a system is producing quality product, notch alignment is becoming an essential feature for achieving quality metrics.
A third means of safeguarding the quality of the chemical process is to process only cassettes that are fully loaded with wafers. If a cassette is uniformly filled to capacity for each process cycle, it is assumed that chemical flow to each wafer is consistent within each process cycle. Although a FOUP contains 25 slots, they are not always presented to the WTS containing a complete set of wafers. Additional FOUPs can be delivered to the WTS to complete a cassette. Alternately, WTS designs may incorporate test wafer stations that contain filler, or dummy, wafers. The WTS automation can access these wafers and load them into a cassette to reach cassette capacity.
Basic Operations in the Related Art
Many systems have been constructed that accomplish the transfer of wafers in keeping with the foregoing discussion. Each of those systems may be described in terms of their subassemblies. It is desirable to simplify the WTS by reducing it to a minimal set of subassemblies, and furthermore to interconnect said subassemblies to operate in an efficient manner.
The main functions of a WTS are to:
unload wafers from a FOUP,
load said wafers into a cassette,
position the wafers vertically for hand-off to the process bench,
unload a processed cassette, and
load processed wafers back into a FOUP.
To minimize contamination, wafer handling tools typically have separate input and output paths for wafer transfer. The input path handles the xe2x80x98dirtyxe2x80x99 wafers, those that have not yet been processed, whereas the output path handles xe2x80x98cleanxe2x80x99 wafers, those that have been processed by the bench. The input path functions are to unload wafers from the FOUP and load cassettes with wafers. Additionally, it is in the input path where notch alignment is performed where applicable. The output path automation unloads processed wafers from cassettes and places them into a FOUP for removal from the tool. Other operations are not restricted to either path and are accessible and utilized by both lines. Functions that may be included in either path include the insertion and removal of test wafers to fill a cassette, and the buffering of cassettes in a storage area.
The transfer begins by supplying wafers to the WTS. The FOUP is set onto a load port at the WTS and the pod door is opened to expose the wafers to the WTS. The WTS automation unloads the wafers one at a time and places them into a cassette. The cassette is an open carrying case including combs for holding the wafers at three or four points of contact. Although the wafers are oriented horizontally in the FOUP, the wafers must be presented to the bench automation in a vertical position (that is, standing on edge) for exposure to process chemicals within the bench. Some WTS designs extract the wafer horizontally, rotate and twist it into a vertical position and then set the wafer down into a horizontally seated cassette. Such a method of transfer increases the potential of damage to each wafer as it undergoes an extensive set of motions before reaching the cassette. Not only is damaged product a concern, but this method also negatively impacts throughput and reliability of the WTS itself by introducing a complicated set of motions.
After the wafers are positioned in the cassette, the bench automation retrieves the cassette and subjects the wafers to chemical processes as dictated by a recipe. When processing is complete, the bench automation delivers the cassette of processed wafers to the WTS. The WTS unloads the processed wafers from the cassette into the FOUP. Once it is completely filled, the operator may remove the FOUP of processed wafers from the load port and introduce another FOUP of unprocessed wafers to continue wafer processing.
In view of the foregoing discussion, the present invention seeks to provide a wafer transfer system that is an improvement over the prior art in the following areas:
it makes more efficient use of floorspace with methods and devices that accomplish more functionality in a smaller footprint;
it offers methods and devices that are inherently more efficient by reducing the number of motions that are necessary to accomplish the required tasks as well as reducing the extent of travel of those motions that remain necessary, thereby increasing throughput;
it increases system reliability by reducing the number of discrete machines; and
it reduces initial capital outlay as well as ongoing maintenance costs by its inherent ability to interface to both left-handed and right-handed process benches.
The wafer transfer system (WTS) of the present invention includes five main subassemblies:
(a) a Load Port,
(b) a Wafer Transfer Robot (WTR),
(c) a Cassette Inversion Mechanism (CIM),
(d) a Test Wafer Station (TWS), and
(e) a Cassette Buffering Station (CBS).
In addition, and as an alternate embodiment of the present invention, the WTS may include an Integrated Notch Aligner (INA).
The WTS and the process bench are integrated so that wafer transfer and processing occur seamlessly. Separate input and output paths are maintained as described above to minimize contamination. The input path automation consists of one Load Port, a WTR, and a CIM. When applicable, notch alignment is performed in the input path by an INA. Automation in the output path includes one Load Port, a WTR without notch alignment capability and a CIM. The CBS and an optional TWS are available to both paths.
Wafers are supplied to the WTS by placing a FOUP onto a Load Port. The Load Port includes an external shelf having a clamping element for holding a FOUP in place for loading and unloading operations. The FOUP may be situated on the Load Port such that the sides of the FOUP case mate with the outside panels of the WTS to prevent contaminants from entering the WTS. The Load Port also includes a Pod Door Opener (PDO), for removing the Front Opening door of the FOUP.
The Wafer Transfer Robot interfaces with the FOUP at the Load Port, with the CIM, and with the TWS. The WTR is a SCARA type robot, known in the art, including y-axis and z-axis translation capability and theta rotation, where the x-axis is taken to be parallel to the plane where the openable face of the FOUP mounts to the Load Port. The WTR includes a substantially horizontal rail that is mounted to a pedestal. The rail lies along a y-axis. The pedestal includes a rail transport mechanism configured to allow vertical translation of the rail in the z-axis. The WTR also includes an arm attached to the rail. The arm is capable of both lateral translation along the y-axis on the rail and theta rotation about a point of attachment of the arm to the rail. In the basic embodiment the arm includes a generally Y-shaped end effector, which is known in the art, for lifting and holding one wafer at a time for transfer by the WTR.
The Cassette Inversion Mechanism (CIM) interfaces with the WTR and the Cassette Buffering Station (CBS). The CIM includes a rotatable pedestal to which a pivotable arm is connected. A cassette holder is connected at a distal end of the pivotable arm. The pivotable arm is capable of vertical translation along a z-axis up and down the rotatable pedestal allowing the cassette holder to be raised or lowered as required for placement of wafers in, or removal of wafers from, the cassette holder by the WTR. The cassette holder includes a cassette locking member for holding the cassette in place in the cassette holder. The cassette holder includes a plurality of grooved fingers for supporting the wafers in the cassette. The CIM has two axes of motion: rotation about a vertical axis and a tilting motion of approximately 90xc2x0 at the pivotable arm to position the cassette in a wafer horizontal orientation for loading or unloading by the WTR, or a wafer vertical orientation for placement of the cassette at, or removal of the cassette from, the cassette buffering station. The CIM can simultaneously position multiple wafers horizontally or vertically with a motion that is coordinated between the rotatable pedestal and the pivotable arm. The CIM may include safety mechanisms designed to indicate that the cassette is firmly held in the CIM. In addition, the CIM is designed such that it can hold any wafer cassette, whether generic or custom. An advantage of the present invention over the prior art is that the CIM provides for simultaneous inversion of multiple wafers in a cassette, therefore increasing reliability and reducing risk of damage to the wafers. Furthermore, the CIM of the present invention increases throughput by facilitating wafer transfer entirely within a horizontal plane.
The Test Wafer Station (TWS) is positioned adjacent to the WTR near the FOUP such that a wafer positioned in the TWS may be retrieved by the WTR. The TWS holds one or more test wafers. Test wafers may be withdrawn from the TWS for placement in a cassette in order to fill the cassette for processing. When processing is complete, the WTR removes the test wafer from the cassette and returns the same test wafer to the TWS.
The Cassette Buffering Station (CBS) of the present invention uses the necessary exchange point with the process bench as a buffer storage area. This approach adds integral cassette storage capacity to the WTS without the separate buffering equipment that is typically purchased and integrated to provide the same functionality. This integral cassette buffering station has the advantage of an overall smaller footprint for the process system. It also requires no additional interfaces and reduces the number of machines required, thereby improving reliability while providing the process bench with an ever-ready supply of cassettes.
In an alternate embodiment of the invention, the WTS includes an Integrated Notch Aligner (INA). The INA is positioned adjacent to the rail of the WTR and is parallel to the rail and the y-axis such that notch alignment can be performed as the WTR is transferring the wafer to the cassette along the y-axis. The INA includes a vacuum chuck located at substantially 90xc2x0 rotation from the face of the FOUP. The vacuum chuck applies suction at a face of the wafer in order to hold the wafer while a drive spins the wafer and a laser or other visioning system locates a wafer notch. This approach improves over the prior art by aligning the wafer within the horizontal path between the FOUP and the cassette without the WTR deviating from that transfer path.